The invention relates to power management, and in particular, to methods of transiting computer power states.
Currently, computers are increasingly conforming to the Advanced Configuration and Power Interface (ACPI) specification.
In computer 100 shown in FIG. 1, Northbridge 120 connects the Central Processing Unit (CPU) 110, main memory 160, and Southbridge 130 through buses. Southbridge 130 connects to Northbridge 120, storage device 140, and peripheral devices 150 through buses. Storage device 140 comprises operating system (OS) 141. Southbridge 130 comprises an arbitrary bit 131, such as the ACPI-defined ARB_DIS bit within the PM2_CNT register.
FIG. 2 is a schematic diagram of ACPI-defined processor power state. A CPU can execute instructions or move data while in a processor working state (C0 state). After computer 100 is idle for a predetermined period, CPU 110 enters one of the later-described power-saving states according to the OS 141, comprising ACPI-defined C1, C2, C3, and other states offering improved power savings over the C3 state, such as C4 state (not shown). The C3 state offers improved power savings over the C1 and C2 states. The C2 state offers improved power savings over the C1 state.
CPU 110 enters the C2 or C3/C4 state according to the bus master activity status of computer 100, such as BM_STS register. A bus master is an element of computer 100 controlling bus paths. When OS 141 determines that computer 100 has been idle for the predetermined period, CPU 110 enters the C3 or C4 state.
In a C2 power state, CPU 110 does not execute instructions but CPU 110 can snoop the bus master accesses to main memory 160. CPU 110 returns from the C2 state to C0 state when a break event occurs, such as an interrupt or an execution request.
In the C3/C4 state, CPU 110 does not snoop the bus master accesses to main memory 160 and further stops the clock.
Before CPU enters the C3/C4 state, arbitrary bit 131 will be turned on (e.g. ARB_DIS is assigned to 1) to prevent sending requests from Northbridge 120 to CPU 110. Thus, bus masters will not violate cache coherency.
CPU 110 must return from C3/C4 state to C0 state upon a break event, for example, when a bus master accesses main memory 160, when CPU 110 is required to execute instructions, or when an interrupt occurs.
Although the C3/C4 state uses less power than the C2 state, request response time in the C3/C4 state is longer than that for the C2 state.
Latency from receiving a request by Southbridge 130 to responding the request by CPU 110 includes the time for returning from the C3/C4 state to the C0 state, disabling arbitrary bit 131, transmitting the request from Southbridge 130 to Northbridge 120, and transmitting the request from Northbridge 120 to CPU 110.
FIG. 3 is a flowchart of conventional power state management procedures. First, when CPU 110 is in the C3/C4 state, Southbridge 130 receives a break event from peripheral devices 150 which CPU 110 needs to execute instructions or move data (step S302). Southbridge 130 directs CPU 110 to transit from the C3/C4 state to the C0 state (step S304). When CPU 110 is in the C0 state, arbitrary bit 131 is disabled (step S306). Southbridge 130 then transmits the request to Northbridge 120 (step S308) Northbridge 120 subsequently transmits the request to CPU 110 (step S310).
Hence, when a request is received in the C3/C4 state, before responding to the request, transiting CPU 110 power state from the C3/C4 state to the C0 state, disabling arbitrary bit 131, and transmitting the request from Southbridge 130 to Northbridge 120 and then to CPU 110 is required. Thus, the response time is considerably long, which may cause sluggish video playback.